Total Experience: 4.5 years Industry + 13 years Academia

NVIDIA, Santa Clara, CA

Reflex Latency Analyzer Engineering Intern

Aug 2021 - Dec 2021

• Worked as part of the GSYNC Reflex Latency Analyser team as an FPGA/firmware engineer responsible for real-time performance metrics of gaming monitors
• Reduced embedded CPU processing load to detect mouse clicks and keyboard taps by adding a hardware USB transaction filter that removes irrelevant USB packets.
• Gained >2x speedup per transaction by designing RTL and the corresponding firmware changes for snooping USB traffic at packet level for recording interesting events such as keyboard taps or mouse clicks.
• Identified performance critical areas that can be improved using debugging and packet sniffing tools like Signal Tap and Wireshark.

Lawrence Livermore National Lab, Livermore, CA

Computational Engineering Division Intern | Dr. Maya Gokhale

May 2019 – Aug 2019

• Built a dynamic delay unit emulator called “Logic in-Memory Emulator (LiME)” on a Zynq Ultrascale+ MPSoC FPGA (Fidus Sidewinder or ZCU102) that allowed engineers in the U.S. Department of Energy to model(emulate) current and future memory systems as well as near memory accelerators
• Got only 20x slower speeds than real time (orders of magnitude faster than typical simulators) execution

Center for Research in Extreme Scale Technologies , IU Bloomington, IN

Research Assistant | Prof. Thomas Sterling

Jun 2017 – Aug 2018